STW18NB40 - ST Microelectronics

STW18NB40 N-CHANNEL MOSFET

Using the latest high voltage MESH OVERLAY ™ process, STMicroelectronics has designed an advanced family of power MOSFETs with outstanding performances. The new patent pending strip layout coupled with the Company’s proprieraty edge termination structure, gives the lowest R DS(on) per area, exceptional avalanche and dv/dt capabilities and unrivalled gate cha.

Features

R VGS ID ID IDM (l) PTOT dv/dt (1) VISO Tstg Tj Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 kΩ) Gate- source Voltage Drain Current (continuos) at TC = 25°C Drain Current (continuos) at TC = 100°C Drain Current (pulsed) Total Dissipation at TC = 25°C Derating Factor Peak Diode Recovery voltage slope Insulation Withstand Voltage (DC) Storage Temperature Max. Operating Junction Temperature INTERNAL SCHEMATIC DIAGRAM Value STW18NB40 400 400 ±30 18.4 11.6 73.6 190 1.52 4.5
  –65 to 150 150 (1)ISD<18.4A, di/dt<200A/µ, VDD