STCCP27A - ST Microelectronics

STCCP27A High speed dual differential line receivers

The STCCP27A receiver converts the subLVDS clock/datastream (up to 416 Mbps throughput bandwidth) back into parallel 8 bits of CMOS/ LVTTL. The device recognizes the CCP 32bit start of frame (SOF), end of frame (EOF), start of line (SOL) and end of line (EOL) sequences to generate the H-SYNC and V-SYNC signals. Output LVTTL clock (up to 52 MHz) is transmitte.

Features

ardous substances) . µTFBGA25 s s s Description The STCCP27A receiver converts the subLVDS clock/datastream (up to 416 Mbps throughput bandwidth) back into parallel 8 bits of CMOS/ LVTTL. The device recognizes the CCP 32bit start of frame (SOF), end of frame (EOF), start of line (SOL) and end of line (EOL) sequences to generate the H-SYNC and V-SYNC signals. Output LVTTL clock (up to 52 MHz) is transmitted in parallel with data. Input and Output data are rising edge strobe. This chipset is an ideal means to link mobile camera modules to baseband processors. In order to minimize static curr.