STA2062A - STMicroelectronics

STA2062A Infotainment application processor

Figure 1. DREQ0 DREQ1 DMA 1 DMA 0 M1 S M0 LCDC Interface ULPI Interface JTAG 16 KB I / 16KB DCACHE USB PHY M0 S M1 ADDRESS CTRL FSMC LCD CTRL VIC (8K x 32) 8K ITCM / 8K DTCM ARM926EJ S USB OTG HS USB FS S S eROM S Description PORT FSMC DATA IM DM S S M ADDRESS ARM AHB Instruction ARM AHB Data DMA 0 M0 S (32K x 32) CTRL S LCD AHB DMA 0/1 .

Features

■
■
■
■
■
■
■
■
■
■
■
■
■
■ High performance ARM926 MCU (up to 333 MHz) MCU memory organization
  – Cache: 16 Kbyte instruction, 16 Kbyte data
  – 8 Kbyte instruction TCM (tightly coupled memory)
  – 8 Kbyte data TCM
  – 32 Kbyte embedded ROM for boot
  – Two banks of 64 Kbyte embedded SRAM
  – 512 Byte embedded SRAM for back-up
  – 4 Gbyte total linear address space
  – Memory extension through: Flexible static memory controller-FSMC (NOR/NAND Flash, CF/CF+, ROM, SRAM support) Mobile DDR/SDRAM controller: 16 bit data @166 MHz, 2 Chip Select, 512 Kbit each Interrupt
  – 64-channel interrupt controller (VIC.