SPC560B50B2 - ST Microelectronics

SPC560B50B2 32-bit MCU family built on the Power Architecture embedded category

. . . . 7 2 3 Block diagram 10 Package pinouts and signal descriptions . . . . . 13 3.1 3.2 Package pinouts . . . . . . . . .

Features

■ High-performance 64 MHz e200z0h CPU
  – 32-bit Power Architecture® technology
  – Up to 60 DMIPs operation
  – Variable length encoding (VLE) Memory
  – Up to 512 Kbytes Code Flash, with ECC
  – 64 Kbytes Data Flash, with ECC
  – Up to 48 Kbytes SRAM, with ECC
  – 8-entry memory protection unit (MPU) Interrupts
  – 16 priority levels
  – Non-maskable interrupt (NMI)
  – Up to 34 ext. int. including 18 wakeup lines GPIO: QFP64/45, QFP100/75, QFP144/123 Timer units
  – 6-channel 32-bit periodic interrupt timers
  – 4-channel 32-bit system timer module
  – System watchdog timer
  – Real-time clock timer 16-bit counter ti.