SN74SSTVF32852 - Texas Instruments

SN74SSTVF32852 24-BIT TO 48-BIT REGISTERED BUFFER

ordering information This 24-bit to 48-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation. All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are edge-controlled circuits, optimized for unterminated DIMM loads, and meet SSTL_2 Class I specifications. The SN74SSTVF32852 operates from a differential clock (CLK and CLK). D.

Features

00-V Human-Body Model (A114-A)
  – 200-V Machine Model (A115-A)
  – 1000-V Charged-Device Model (C101) description/ordering information This 24-bit to 48-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation. All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are edge-controlled circuits, optimized for unterminated DIMM loads, and meet SSTL_2 Class I specifications. The SN74SSTVF32852 operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low. The device supports low-power standby operation. When RE.