SN54AS286 - Texas Instruments

SN54AS286 9-Bit Parity Generators/Checker

SN54AS286, SN74AS286 9ĆBIT PARITY GENERATORS/CHECKERS WITH BUSĆDRIVER PARITY I/O PORT SDAS050B − DECEMBER 1983 − REVISED DECEMBER 1994 SN54AS286 . . . J PACKAGE SN74AS286 . . . D OR N PACKAGE (TOP VIEW) G1 H2 XMIT 3 I4 PARITY ERROR 5 PARITY I/O 6 GND 7 14 VCC 13 F 12 E 11 D 10 C 9B 8A SN54AS286 . . . FK PACKAGE (TOP VIEW) The SN54AS286 and SN74AS286 uni.

Features

emented specifically to accommodate cascading. When XMIT is low, the parity tree is disabled and PARITY ERROR remains at a high logic level regardless of the input levels. When XMIT is high, the parity tree is enabled. PARITY ERROR indicates a parity error when either an even number of inputs ( A−I ) are high and PARITY I/O is forced to a low logic level, or when an odd number of inputs are high and PARITY I/O is forced to a high logic level. H XMIT NC I NC PARITY ERROR 3 2 1 20 19 4 18 E 5 17 NC 6 16 D 7 15 NC 8 14 C 9 10 11 12 13 B A NC GND PARITY I/O NC − No internal co.