SM5902AF - Nippon Precision Circuits Inc

SM5902AF compression and non compression type shock-proof memory controller

Pin number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Pin name VDD2 UC1 UC2 UC3 UC4 UC5 DIT NTEST CLK VSS YSRDATA YLRCK YSCK ZSCK ZLRCK ZSRDATA YFLAG YFCLK YBLKCK NRESET ZSENSE VDD1 YDMUTE YMLD YMDATA YMCLK A10 (NCAS2) NCAS D2 D3 D0 D1 NWE NRAS A9 A8 A7 A6 A5 A4 A0 A1 A2 A3 I/O I.

Features

- 2-channel processing - Serial data input ⋅ 2s complement, 16-bit/MSB first, right-justified format ⋅ Wide capture function (up to 3 × speed input rate) - System clock input ⋅ 384fs (16.9344 MHz) - Shock-proof memory controller ⋅ ADPCM compression method ⋅ 4-level compression mode selectable 4-bit compression mode 2.78 s/Mbit 5-bit compression mode 2.22 s/Mbit 6-bit compression mode 1.85 s/Mbit Full-bit non compression mode 0.74 s/Mbit ⋅ 4 external DRAM configurations selectable 1 × 16M DRAM (4M × 4 bits, refresh cycle = 2048 cycle) 1 × or 2 × 4M DRAM (1M × 4 bits) 1 × 1M DRAM (256k × 4 bits).