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SI5330 - Silicon Laboratories

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SI5330 LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR

. . . . . . .9 3.1. VDD and VDDO Supplies .9 3.2. Loss Of Signal Indicator (LOS) . . . . . .9 3.3. Output En.

Features





 18 17 16 15 14 13 7 8 9 10 11 12
 Supports single-ended or differential input clock signals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs Provides signal level translation
Differential to single-ended
Single-ended to differential
Differential to differential
Single-ended to single-ended Wide frequency range
LVPECL, LVDS: 5 to 710 MHz
HCSL: 5 to 250 MHz
SSTL, HSTL: 5 to 350 MHz
CMOS: 5 to 200 MHz Additive jitter: 150 fs RMS typ







 RSVD_GND CLK0A CLK0B VDD VDDO0 20
 Small size: 24-lead, 4 x 4.

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