S2068 - AMCC

S2068 DUAL GIGABIT ETHERNET TRANSCEIVER

The S2068 dual transmitter and receiver chip is designed to provide two channels of high-speed serial data transmission over fiber optic or copper interfaces conformi.

Features

• Functionally compliant with IEEE 802.3z Gigabit Ethernet Applications
• 1250 MHz (Gigabit Ethernet) operating rate
  – Half rate operation
• Dual Transmitter incorporating phase-locked loop (PLL) clock synthesis from low speed reference
• Dual Receiver PLL provides clock and data recovery
• Internally series terminated TTL outputs
• Low-jitter serial PECL interface
• Local Loopback
• Interfaces with coax, twinax, or fiber optics
• Single +3.3V supply, 1.37W power dissipation
• Compact 21mm x 21mm 156 TBGA package APPLICATIONS High-speed data communications
• Ethernet Backbones
• Multi-port Gig.