S2042 - AMCC

S2042 (S2042 / S2043) HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS

S2042/S2043 S2042/S2043 FEATURES • Functionally compliant with ANSI X3T11 Fibre Channel physical and transmission protocol standards • S2042 transmitter incorporates phase-locked loop (PLL) providing clock synthesis from low-speed reference • S2043 receiver PLL configured for clock and data recovery • 1062, 531 and 266 Mb/s operation • 10- or 20-bit parall.

Features

• Functionally compliant with ANSI X3T11 Fibre Channel physical and transmission protocol standards
• S2042 transmitter incorporates phase-locked loop (PLL) providing clock synthesis from low-speed reference
• S2043 receiver PLL configured for clock and data recovery
• 1062, 531 and 266 Mb/s operation
• 10- or 20-bit parallel TTL compatible interface
• 1 watt typical power dissipation for chipset
• +3.3/+5V power supply
• Low-jitter serial PECL compatible interface
• Lock detect
• Local loopback
• 10mm x 10mm 52 PQFP package
• Fibre Channel framing performed by receiver
• Continuous downstream.