RX62G - Renesas

RX62G 100-MHz 32-bit RX MCUs

 Maximum operating frequency: 100MHz  32-bit RX CPU  Minimum instruction execution time: One instruction per state (cycle of the system clock)  Address space: 4-Gbyte linear  Register set of the CPU  General purpose: Sixteen 32-bit registers  Control: Nine 32-bit registers  Accumulator: One 64-bit register  Basic instructions: 73  Floating-point in.

Features

■ 32-bit RX CPU core
 Max. operating frequency: 100 MHz Capable of 165 DMIPS in operation at 100 MHz
 Single precision 32-bit IEEE-754 floating point
 Accumulator handles 64-bit results (for a single instruction) from 32- × 32-bit operations
 Multiplication and division unit handles 32- × 32-bit operations (multiplication instructions take one CPU clock cycle)
 Fast interrupt
 Divider (fastest instruction execution takes two CPU clock cycles)
 Fast interrupt
 CISC Harvard architecture with 5-stage pipeline
 Variable-length instructions: Ultra-compact code
 Supports the memory protect.