CPU CPU Maximum operating frequency: 50 MHz 32-bit RX CPU Minimum instruction execution time: One instruction per state (cycle of the system clock) Address space: 4-Gbyte linear Register set General purpose: Sixteen 32-bit registers Control: Eight 32-bit registers Accumulator: One 64-bit register Basic instructions: 73 DSP instructions: 9 .
■ 32-bit RX CPU core
Max. operating frequency: 50 MHz Capable of 78 DMIPS in operation at 50 MHz
Accumulator handles 64-bit results (for a single instruction) from 32- × 32-bit operations
Multiplication and division unit handles 32- × 32-bit operations (multiplication instructions take one CPU clock cycle)
Fast interrupt
CISC Harvard architecture with 5-stage pipeline
Variable-length instructions, ultra-compact code
Memory protection unit
On-chip debugging circuit
■ Low power design and architecture
Operation from a single 1.8-V to 3.6-V supply (2.7 V to 3.6 V for the ΔΣ A/D .
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | R5F521A6BGFM |
Renesas |
MCUs | |
2 | R5F521A6BGFN |
Renesas |
MCUs | |
3 | R5F521A6BDFM |
Renesas |
MCUs | |
4 | R5F521A6BDFN |
Renesas |
MCUs | |
5 | R5F521A6BDFP |
Renesas |
MCUs | |
6 | R5F521A6BDLJ |
Renesas |
MCUs | |
7 | R5F521A7BDFM |
Renesas |
MCUs | |
8 | R5F521A7BDFN |
Renesas |
MCUs | |
9 | R5F521A7BDFP |
Renesas |
MCUs | |
10 | R5F521A7BDLJ |
Renesas |
MCUs | |
11 | R5F521A7BGFM |
Renesas |
MCUs | |
12 | R5F521A7BGFN |
Renesas |
MCUs |