R5F51303AGFK - Renesas

R5F51303AGFK 32-bit RX MCUs

CPU CPU  Maximum operating frequency: 32 MHz  32-bit RX CPU  Minimum instruction execution time: One instruction per clock cycle  Address space: 4-Gbyte linear  Register set General purpose: Sixteen 32-bit registers Control: Eight 32-bit registers Accumulator: One 64-bit registers  Basic instructions: 73 (variable-length instruction format)  DSP in.

Features

■ 32-bit RX CPU core
 Max. operating frequency: 32 MHz Capable of 50 DMIPS in operation at 32 MHz
 Accumulator handles 64-bit results (for a single instruction) from 32-bit × 32-bit operations
 Multiplication and division unit handles 32-bit × 32-bit operations (multiplication instructions take one CPU clock cycle)
 Fast interrupt
 CISC Harvard architecture with 5-stage pipeline
 Variable-length instructions, ultra-compact code
 On-chip debugging circuit
■ Low power design and architecture
 Operation from a single 1.8-V to 5.5-V supply
 Three low power consumption modes
 Low power ti.