R1100 - RDC Semiconductor

R1100 16 Bit RISC Micro Processor

RDC ® www.DataSheet4U.com RISC DSP Communication R1100 16 Bit RISC Micro Processor R1100 Brief Sheet 16 BIT RISC MICRO PROCESSOR Specifications subject to change without notice, contact your sales representatives for the most update information. RDC Confidential Page 1 of 5 REV 1.0 May. 04 2007 RDC ® 1 l www.DataSheet4U.com RISC DSP Communication R1.

Features

CPU Core - RDC’s proprietary RISC architecture - Five-stages pipeline - Operation frequency: 80MHz - Support CPU ID - Supports 32 PIO pins - External bus, Internal bus and core in the same clock base l l l l Interrupt Controller - The interrupt controller with seven maskable external interrupts and one non-maskable external interrupt (NMI) Two Independent DMA Channels Integrate PLL(
*1~
*8) Programmable Chip-select Logic - Programmable chip-select logic for Memory or I/O bus cycle decoder l l Programmable Wait-state Generator Counter/Timers - Three independent 16-bit timers and one independent p.