PEF20550 - Infineon Technologies AG

PEF20550 ICs for Communications

(extended) Extensions for V1.3 Arbiter state machine description (extended) Table 14: Control channel delay examples (extended) Internal reference clock RCL replaced by CFI reference clock CRCL Interrupt driven transmission sequence example, figure 50 (new) Internal reference clock RCL replaced by CFI reference clock CRCL Register address arrangement (extend.

Features

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Pin Configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 System Integration and Application . . . . . . . . . . . . . . . . . . . . . . . . . . .