PCS3P623Z09A - PulseCore Semiconductor

PCS3P623Z09A Timing-Safe Peak EMI reduction IC

PCS3P623Z05/09 is a versatile, 3.3V Zero-delay buffer memory interface systems. General Block Diagram PLL CLKIN DLY_CTRL CLKOUT1 CLKOUT2 CLKOUT3 PLL CLKIN MUX DLY_CTRL CLKOUTA1 CLKOUTA2 CLKOUTA3 CLKOUTA4 PCS3P623Z05A/B CLKOUT4 S2 S1 Select Input Decoding CLKOUTB1 CLKOUTB2 CLKOUTB3 PCS3P623Z09A/B CLKOUTB4 PulseCore Semiconductor Corporation 1715 .

Features

•
•
• Clock distribution with Timing-Safe™ Peak EMI Reduction Input frequency range: 20MHz - 50MHz Multiple low skew Timing-safe™ Outputs: PCS3P623Z05: 5 Outputs PCS3P623Z09: 9 Outputs
•
•
•
• External Input-Output Delay Control option Supply Voltage: 3.3V±0.3V Commercial and Industrial temperature range Packaging Information: ASM3P623Z05: 8 pin SOIC, and TSSOP ASM3P623Z09:16 pin SOIC, and TSSOP
• True Drop-in Solution for Zero Delay Buffer, ASM5P2305A / 09A designed to distribute Timing-Safe™ clocks with Peak EMI reduction. PCS3P623Z05 is an eight-pin version, accepts one reference input and.