P2V28S40ATP-8 - Vanguard International Semiconductor

P2V28S40ATP-8 128Mb SDRAM

P2V28S20ATP is organized as 4-bank x 8,388,608-word x 4-bit Synchronous DRAM with LVTTL interface and P2V28S30ATP is organized as 4-bank x 4,194,304-word x 8-bit and P2V28S40ATP is organized as 4-bank x 2,097, 152-word x 16-bit. All inputs and outputs are referenced to the rising edge of CLK. P2V28S20ATP,P2V28S30ATP and P2V28S40ATP achieve very high speed da.

Features

ITEM tCLK tRAS tRCD tAC tRC Icc1 Clock Cycle Time (Min.) CL=2 CL=3 -7 7ns 45ns CL=2 CL=3 V28S20D 20ns 5.4ns 63ns 85mA 85mA 85mA 1mA P2V28S20/30/40ATP -75 -8 10ns 7.5ns 45ns 20ns 6ns 5.4ns 67.5ns 85mA 85mA 85mA 1mA 10ns 8ns 48ns 20ns 6ns 6ns 70ns 85mA 85mA 85mA 1mA Active to Precharge Command Period (Min.) (Min.) Row to Column Delay Access Time from CLK Ref /Active Command Period Operation Current (Single Bank) (Max.) (Min.) (Max.) V28S30D V28S40D -7,-75,-8 Icc6 Self Refresh Current (Max.) - Single 3.3V ±0.3V power supply - Max. Clock frequency -7:143MHz<3-3-3>/-75:133MHz<3-3-3>/-8:100MH.