NT5CC128M16HP - Nanya

NT5CC128M16HP 2Gb DDR3 SDRAM H-Die

The 2Gb Double-Data-Rate-3 (DDR3(L)) H-die DRAM is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAMs. The 2Gb chip is organized as 16Mbit x 16 I/Os x 8 bank devices. These synchronous devices achieve high speed double-data-rate transfer rates of up to 2133 Mb/sec/pin for general applications. Th.

Features

and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous fashion. These devices operate with a single 1.5V ± 0.075V or 1.35V -0.067V/+0.1V power supply and are available in BGA packages. 3 REV 1.4 02 /2013 © NANYA TECHNOLOGY CORP. All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. Free.