Pin Name I/O Description 1 Q1 LVDS Output Non−inverted IN output. Typically loaded with 100 W receiver termination resistor across differential pair. 2 Q1 LVDS Output Inverted IN output. Typically loaded with 100 W receiver termination resistor across differential pair. 3 Q2 LVDS Output Non−inverted IN output. Typically loaded with 100 W receiver.
• Maximum Input Clock Frequency > 2.0 GHz
• Maximum Input Data Rate > 2.5 Gb/s
• 1 ps Maximum of RMS Clock Jitter
• Typically 10 ps of Data Dependent Jitter
• 380 ps Typical Propagation Delay
• 120 ps Typical Rise and Fall Times
• Single Power Supply; VCC = 2.5 $ 5%
• VREF_AC Reference Output
• These are Pb−Free Devices
Device DDJ = 10 ps
http://onsemi.com
1
QFN−16 MN SUFFIX CASE 485G
MARKING DIAGRAM
*
16
1
NB6L 14S ALYW G
G
A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to .
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | NB6L14 |
ON Semiconductor |
Differential 1:4 LVPECL Fanout Buffer | |
2 | NB6L14M |
ON Semiconductor |
Differential 1:4 CML Fanout Buffer | |
3 | NB6L11 |
ON Semiconductor |
2.5V / 3.3V MULTILEVEL INPUT TO DIFFERENTIAL LVPECL/LVNECL | |
4 | NB6L11M |
ON Semiconductor |
Differential CML Fanout Buffer | |
5 | NB6L11S |
ON Semiconductor |
Input to LVDS Fanout Buffer/Translator | |
6 | NB6L16 |
ON Semiconductor |
6GHz/6Gbps 2.5V/3.3V Multi-level Input to Differential Lvecl Clock or Data Translator/receiver/driver Buffer | |
7 | NB6L239 |
ON Semiconductor |
2.5V / 3.3V Any Differential Clock IN to Differential LVPECL OUT Clock Divider | |
8 | NB6L295 |
ON Semiconductor |
2.5V / 3.3V Dual Channel Programmable Clock/Data Delay | |
9 | NB6L295M |
ON Semiconductor |
2.5V / 3.3V Dual Channel Programmable Clock/Data Delay | |
10 | NB6L56 |
ON Semiconductor |
2.5V / 3.3V Dual 2:1 Differential Clock / Data Multiplexer | |
11 | NB6L572M |
ON Semiconductor |
2.5V / 3.3V Differential 4:1 Mux To 1:2 CML Clock/Data Fanout / Translator | |
12 | NB6L611 |
ON Semiconductor |
Differential LVPECL Clock / Data Fanout Buffer |