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NB6L14S - ON Semiconductor

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NB6L14S 2.5V 1:4 AnyLevel Differential Input to LVDS Fanout Buffer/Translator

Pin Name I/O Description 1 Q1 LVDS Output Non−inverted IN output. Typically loaded with 100 W receiver termination resistor across differential pair. 2 Q1 LVDS Output Inverted IN output. Typically loaded with 100 W receiver termination resistor across differential pair. 3 Q2 LVDS Output Non−inverted IN output. Typically loaded with 100 W receiver.

Features


• Maximum Input Clock Frequency > 2.0 GHz
• Maximum Input Data Rate > 2.5 Gb/s
• 1 ps Maximum of RMS Clock Jitter
• Typically 10 ps of Data Dependent Jitter
• 380 ps Typical Propagation Delay
• 120 ps Typical Rise and Fall Times
• Single Power Supply; VCC = 2.5 $ 5%
• VREF_AC Reference Output
• These are Pb−Free Devices Device DDJ = 10 ps http://onsemi.com 1 QFN−16 MN SUFFIX CASE 485G MARKING DIAGRAM
* 16 1 NB6L 14S ALYW G G A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location)
*For additional marking information, refer to .

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