MTD8N06E - Motorola

MTD8N06E TMOS POWER FET

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MTD8N06E/D Designer's TMOS E-FET .™ Power Field Effect Transistor DPAK for Surface Mount N–Channel Enhancement–Mode Silicon Gate This advanced TMOS E–FET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drain–to–source di.

Features

500 Unit Tape & Reel, Add T4 Suffix to Part Number ™ Data Sheet MTD8N06E TMOS POWER FET 8.0 AMPERES 60 VOLTS RDS(on) = 0.12 OHM ® D G S CASE 369A
  –13, Style 2 DPAK MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Drain
  –Source Voltage Drain
  –Gate Voltage (RGS = 1.0 MΩ) Gate
  –Source Voltage — Continuous Gate
  –Source Voltage — Non
  –Repetitive (tp ≤ 10 ms) Drain Current — Continuous — Continuous @ 100°C — Single Pulse (tp ≤ 10 µs) Total Power Dissipation Derate above 25°C Total Power Dissipation @ TA = 25°C, when mounted to minimum recommended pad size Operating and Storage Temperatur.