MT8LSDT3264A - Micron Technology

MT8LSDT3264A SYNCHRONOUS DRAM MODULE

SYMBOL RAS#, CAS#, WE# CK0-CK3 TYPE Input Input DESCRIPTION Command Inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. Clock: CK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CK. CK also increments the internal burst counter and controls the output registers. Clock Enable: CKE activates.

Features

• PC100- and PC133-compliant
• JEDEC-standard 168-pin, dual in-line memory module (DIMM)
• Unbuffered
• 256MB (32 Meg x 64), 512MB (64 Meg x 64)
• Single +3.3V ±0.3V power supply
• Fully synchronous; all signals registered on positive edge of system clock
• Internal pipelined operation; column address can be changed every clock cycle
• Internal SDRAM banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, including Concurrent Auto Precharge, and Auto Refresh Modes
• 64ms, 8,192 cycle Auto Refresh cycle
• Self Refresh Mode
• LVTTL-compatibl.