MSC220 - Zarlink Semiconductor

MSC220 XpressFlow 2020 Ethernet Routing Switch Chipset

The XpressFlow Engine contains the switching data base interface and buffer management logic in order to do the switching decision making for unicast, multicast, and broadcast frames. Hardware assisted queue manager is incorporated to facilitate buffer management. It also provides a generic Management Bus interface to allow external processor to do initializ.

Features

agement Bus I/O interface ◊ ◊ ◊ Allows host to access CAM and Control Buffer Memory Supports Big and Little Endian CPUs Direct interface with various different standard microprocessors including 386, 486 families and Motorola MPC series embedded processors Switching bandwidth 32 XpressFlow BUS 32 XpressFlow BUS t 32-bit XpressFlow Bus Interface ◊ −1.28 Gbps @ 40 MHz system clock −1.60 Gbps @ 50 MHz system clock −2.10 Gbps @ 66.67 MHz system clock ◊ ◊ ◊ Supports up to 8 Multi-port Network Access Controllers XpressFlow Bus access arbitration XpressFlow Bus data transfer load regulation Addre.