MPC8569E - NXP

MPC8569E PowerQUICC III Integrated Processor Hardware Specifications

Freescale Semiconductor Data Sheet: Technical Data MPC8569E PowerQUICC III Integrated Processor Hardware Specifications Document Number: MPC8569EEC Rev. 2, 10/2013 MPC8569E • High-performance, 32-bit e500 core, scaling up to 1.33 GHz, that implements the Power Architecture® technology – 2799 MIPS at 1.33 GHz (estimated Dhrystone 2.1) – 36-bit physical addr.

Features

e
  – Invoke a level of system power management by asserting MCKE SDRAM signal on-the-fly to put the memory into a low-power sleep mode
  – Both hardware and software options to support battery-backed main memory
  – Initialization bypass feature that allow system designers to prevent re-initialization of main memory during system power on following abnormal shutdown
• Integrated security engine (SEC) optimized to process all the algorithms associated with IPsec, IKE, SSL/TLS, iSCSI, SRTP, IEEE Std 802.11i™, IEEE Std 802.16™ (WiMAX), IEEE 802.1ae™ (MACSec), 3GPP, A5/3 for GSM and EDGE, and GEA3 for .