This high speed 10-to-4 Line Priority Encoder utilizes advanced silicon-gate CMOS technology It possesses the high noise immunity and low power consumption of standard CMOS integrated circuits This device is fully buffered giving it a fanout of 10 LS-TTL loads The MM54HC147 MM74HC147 features priority encoding of the inputs to ensure that only the highest or.
priority encoding of the inputs to ensure that only the highest order data line is encoded Nine input lines are encoded to a four line BCD output The implied decimal zero condition requires no input condition as zero is encoded when all nine data lines are at a high logic level All data inputs and outputs are active at the low logic level The 54HC 74HC logic family is functionally as well as pinout compatible with the standard 54LS 74LS logic family All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground Features Y Y Y Y Low quiescent power con.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | MM74HC14 |
Fairchild |
Hex Inverting Schmitt Trigger | |
2 | MM74HC148 |
Fairchild |
8-3 Line Priority Encoder | |
3 | MM74HC148 |
National Semiconductor |
8-3 Line Priority Encoder | |
4 | MM74HC11 |
National |
Triple 3-Input AND Gate | |
5 | MM74HC112 |
National Semiconductor |
Dual J-K Flip-Flop | |
6 | MM74HC123A |
National Semiconductor |
Dual Retriggerable Monostable Multivibrator | |
7 | MM74HC123A |
Fairchild |
Dual Retriggerable Monostable Multivibrator | |
8 | MM74HC125 |
Fairchild |
3-STATE Quad Buffers | |
9 | MM74HC125 |
ON Semiconductor |
3-STATE Quad Buffers | |
10 | MM74HC126 |
Fairchild Semiconductor |
3-STATE Quad Buffers | |
11 | MM74HC126 |
ON Semiconductor |
3-STATE Quad Buffers | |
12 | MM74HC132 |
Fairchild |
Quad 2-Input NAND Schmitt Trigger |