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The MK2049-36 is a Phase-Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-36 generates T1, E1, T3, E3, OC3/3, Gigabit Ethernet, and other communications frequencies. This allows for the generation of clocks frequency-locked to an 8 kHz backplane clock, simplifying clock sy.
• Packaged in 20 pin SOIC
• 3.3 V ±5% operation
• Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E
• Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz
• Locks to 8 kHz ±100 ppm (External mode)
• Buffer Mode allows jitter attenuation of 10-50 MHz input and x1/x0.5 or x1/x2 outputs
• Exact internal ratios enable zero ppm error
• Output clock rates include T1, E1, T3, E3, and OC3 submultiples
• See the MK2049-01, -02, and -03 for more selections at VDD = 5 V, and the MK2049-34 f.
MK2049-36 - Renesas
The MK2049-36 is a Phased Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies. With an 8 k.
| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
| 1 | MK2049-34 |
Integrated Circuit Systems |
3.3 V Communications Clock PLL |
|
| 2 | MK2049-34 |
Renesas |
CLOCK VCXO PLL |
|
| 3 | MK2049-34A |
Integrated Circuit Systems |
3.3 Volt Communications Clock VCXO PLL |
|
| 4 | MK2049-35 |
Integrated Circuit Systems |
3.3 V Communications Clock PLL |
|
| 5 | MK2049-01 |
Integrated Circuit Systems |
Communications Clock PLL |
|
| 6 | MK2049-02 |
Integrated Circuit Systems |
Communications Clock PLLs |
|
| 7 | MK2049-03 |
Integrated Circuit Systems |
Communications Clock PLLs |
|
| 8 | MK2049-45 |
Integrated Circuit Systems |
3.3V Communications Clock PLL |
|
| 9 | MK2049-45 |
Renesas |
CLOCK PLL |
|
| 10 | MK2049-45 |
Renesas |
CLOCK PLL |
|
| 11 | MK2042-01 |
Integrated Circuit Systems |
Communications Clock Monitor |
|
| 12 | MK2011 |
Integrated Circuit Systems |
Fast Ethernet Clock Source |
|