MG82FE532 - Megawin

MG82FE532 8051-Based MCU

8051-Based MCU MG82FE/L532 Data Sheet Version: A1.01 This document contains information on a new product under development by Megawin. Megawin reserves the right to change or discontinue this product without notice.  Megawin Technology Co., Ltd. 2012 All rights reserved. 2015/09 version A1.01 2 MG82FE/L532 Data Sheet MEGAWIN Features  Enhanced 80C5.

Features

 Enhanced 80C51 Central Processing Unit
 64K bytes of MG82Fx532 on-chip flash memory with ISP/IAP capability ━ ISP memory zone as 1.5KB(default) ━ Flexible IAP size. 30.5KB(default) ━ Code protection for flash memory access Part No. AP Flash ROM size IAP size MG82Fx532 32KB (Max.) 30.5KB (Min.)
 256 bytes scratch-pad RAM and 1024 bytes expanded RAM (XRAM)
 Dual data pointer.
 Variable length MOVX for slow SRAM or peripherals.
 Three 16-bit timer/counter, Timer 0, Timer 1 and Timer 2. ━ T0CKO on P34, T1CKO on P35 and T2CKO on P10 ━ X12 mode enabled for T0/T1/T2.
 Programmable .