MC74HC112A Dual J-K Flip-Flop with Set and Reset High−Performance Silicon−Gate CMOS The MC74HC112A is identical in pinout to the LS112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Each flip−flop is negative−edge clocked and has active−low asynchronous Set and Reset inputs. The H.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Similar in Function to the LS112 Except When Set and Reset are
Low Simultaneously
• Chip Complexity: 100 FETs or 25 Equivalent Gates
• These are Pb−Free Devices
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MARKING DIAGRAMS
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SOIC−16 D SUFFIX CASE 751B
HC112AG AWLYWW
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TSSOP−16 DT SUFFIX CASE 948F
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HC 112A ALYWG
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No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | MC74HC11 |
Motorola |
Triple 3-Input AND Gate | |
2 | MC74HC11A |
Motorola |
Triple 3-Input AND Gate | |
3 | MC74HC11A |
ON Semiconductor |
Triple 3-Input AND Gate | |
4 | MC74HC10A |
ON Semiconductor |
Triple 3-Input NAND Gate | |
5 | MC74HC125A |
ON Semiconductor |
Quad 3-State Noninverting Buffers | |
6 | MC74HC125A |
Motorola |
Quad 3-State Noninverting Buffers | |
7 | MC74HC125N |
ETC |
CMOS Bus Buffer Gates | |
8 | MC74HC126A |
ON Semiconductor |
Quad 3-State Noninverting Buffers | |
9 | MC74HC126A |
Motorola |
Quad 3-State Noninverting Buffers | |
10 | MC74HC132A |
Motorola |
Quad 2-Input NAND Gate | |
11 | MC74HC132A |
ON Semiconductor |
Quad 2-Input NAND Gate | |
12 | MC74HC133 |
Motorola |
13-Input NAND Gate |