MBL8289-1 - Fujitsu

MBL8289-1 BIPOLAR BUS ARBITER

TABLE 1 - PIN DESCRIPTION Symbol Type Name and Function Vee GND SO, Sl, S2 ClK lOCK CRQlCK RESB ANYRQST lOB Power: +5V supply ±10%. Ground. I Status Input Pins: The status input pins from an MBl8086, MBl 8088, MBl80186, MBl80188 or MBl8089 processor. The MBl8289 decodes these pins to initiate bus request and surrender actions. (See Table 2.) I Clock: Fro.

Features

tions: - 20-Pin Cerdip (Suffix: -CZ) - 20-Pin Plastic DIP (Suffix: -PI Fig. 1 - BLOCK DIAGRAM MBl80861 { 52 ~~t:g:~1 Sf STATUS SO 1 PROCESSOR lOCK ClK CROlCK CONTROL RESB ANYROST lOB INIT BClK BREO BPRN BPRO BUSY CBRO MUlTlBUS' COMMAND SIGNALS ~~;~!~s AEN } L __-=::::;;::::::::::::;r:::::::::::::::::::t-SYSB/RESB Fig. 2 - PIN CONFIGURATION +5V GND Fig. 3 - FUNCTIONAL PINOUT 52 lOB SYSB/RESB BClK iNTI' vee ClK lOCK CROlCK ANYROST AEN 'CB'RCi BUSY GND PROCESSOR { STATUS OO~'OU STRAPPING { OPTIONS vee INIT BClK BREO BPRN BPACi BUSY CBRD MUlTIBUS INTERFACE SYSB/RESB } SYSTE.