The M54/74HCT165 is a high speed CMOS 8 BIT PISO SHIFT REGISTER fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. It achives the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. This device contains eight clocked master .
entrens when the shift/load input is low. The parallel data can change while shift/load is low, provided that the recommended set-up and hold times are observed. For clocked operation, shift/load must be high. The two clock input perform identically; one can be used as a clock inhibit by applying a high signal; to permit this operation clocking is accomplished through a 2 input nor gates. To avoid double clocking, however, the inhibit signal should only go high while the clock is high. Otherwise the rising inhibit signal will cause the same response as rising clock edge.This integrated circuit.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | M74HCT160 |
ST Microelectronics |
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER | |
2 | M74HCT161 |
ST Microelectronics |
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER | |
3 | M74HCT162 |
ST Microelectronics |
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER | |
4 | M74HCT163 |
ST Microelectronics |
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER | |
5 | M74HCT164 |
ST Microelectronics |
8 BIT SIPO SHIFT REGISTER | |
6 | M74HCT10 |
ST Microelectronics |
TRIPLE 3-INPUT NAND GATE | |
7 | M74HCT125 |
ST Microelectronics |
QUAD BUS BUFFERS | |
8 | M74HCT126 |
ST Microelectronics |
QUAD BUS BUFFERS | |
9 | M74HCT132 |
ST Microelectronics |
QUAD 2-INPUT SCHMITT NAND GATE | |
10 | M74HCT137 |
ST Microelectronics |
3 TO 8 LINE DECODER/LATCH INVERTING | |
11 | M74HCT138 |
ST Microelectronics |
3 TO 8 LINE DECODER INVERTING | |
12 | M74HCT139 |
ST Microelectronics |
DUAL 2 TO 4 DECODER/DEMULTIPLEXER |