Pin Name A0 ~ A12 BA0 ~ BA1 DQ0 ~ DQ63 DQS0 ~ DQS17 CK0,CK0 ~ CK2, CK2 CKE0, CKE1(for double banks) CS0, CS1(for double banks) RAS CAS WE CB0 ~ CB7 Function Address input (Multiplexed) Bank Select Address Data input/output Data Strobe input/output Clock input Clock enable input Chip select input Row address strobe Column address strobe Write enable Check bit.
2.5V ± 0.2V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency 2, 2.5 (clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
• Serial presence detect with EEPROM
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
R.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | M312L2923BG0-A2 |
Samsung |
DDR SDRAM Registered Module | |
2 | M312L2923BG0-CB3 |
Samsung |
DDR SDRAM Registered Module | |
3 | M312L2923BTS-A2 |
Samsung |
DDR SDRAM Registered Module | |
4 | M312L2923BTS-CAA |
Samsung |
DDR SDRAM Registered Module | |
5 | M312L2920BG0 |
Samsung |
DDR SDRAM Registered Module | |
6 | M312L2920BG0-A2 |
Samsung |
DDR SDRAM Registered Module | |
7 | M312L2920BG0-B0 |
Samsung |
DDR SDRAM Registered Module | |
8 | M312L2920BG0-CB3 |
Samsung |
DDR SDRAM Registered Module | |
9 | M312L2920BT |
Samsung |
DDR SDRAM Registered Module | |
10 | M312L2920BTS-A2 |
Samsung |
DDR SDRAM Registered Module | |
11 | M312L2920BTS-CAA |
Samsung |
DDR SDRAM Registered Module | |
12 | M312L2920GH3-CB3 |
Samsung |
DDR SDRAM Registered DIMM |