LV8071LP - Sanyo Electric

LV8071LP Piezoelectric Actuator Driver IC

of the Operation • CLK1 and CLK2 inputs CLK1 incorporates the quarter-dividing circuit. To input 39MHz directly, input it directly to the CLK1 pin. When the dividing circuit is provided externally, input 9.75MHz to the CLK2 pin. Short-circuit the unused CLK pin to GND. • 1 cycle: One cycle (8.923μs for CLK1=39MHz or CLK2=9.75MHz) of OUT waveform operation is.

Features

The actuator using the piezoelectric device is driven by the external CLK input and simple control signal.
• The 39MHz (CLK1 pin input) CLK input is divided into quarters internally to generate the 9.75MHz input. The operation time is generated using this as a base CLK to ensure the output appropriate for piezoelectric drive. The CLK2 input of 9.75MHz is input to be used, as it is, for the base CLK either.
• IC start/stop is controlled by the EN input. Initialization is made according to the built-in sequence at startup.
• The actuator drive time is determined by inputting the pulse to the DRI.