LMA1009 - LOGIC Devices Incorporated

LMA1009 12 x 12-bit Multiplier-Accumulator

Data present at the A and B input registers is latched on the rising edges of CLK A and CLK B respectively. RND, TC, ACC, and SUB controls are latched on the rising edge of the logical OR of CLK A and CLK B. TC specifies the input as two’s complement (TC HIGH) or unsigned magnitude (TC LOW). RND, when HIGH, adds ‘1’ to the most significant bit position of th.

Features

u 20 ns Multiply-Accumulate Time u Low Power CMOS Technology u Replaces Fairchild TDC1009/ TMC2009 u Two’s Complement or Unsigned Operands u Accumulator Performs Preload, Accumulate, and Subtract u Three-State Outputs u 68-pin PLCC, J-Lead LMA1009/2009 BLOCK DIAGRAM CLK A CLK B TC ACC SUB REGISTER RND OEX OEM OEL PREL 3 OEX OEM OEL PRELOAD CONTROL LOGIC 3 LEX LEM LEL R
  – A PASS R The LMA1009/2009 output register (accumulator register) is divided into three independently controlled sections. The least significant result (LSR) and most significant result (MSR) registers are 12 bits in l.