LCMXO2-1200ZE - Lattice

LCMXO2-1200ZE MachXO2

MachXO2™ Family Data Sheet DS1035 Version 3.3, March 2017 MachXO2 Family Data Sheet Introduction May 2016 Data Sheet DS1035 Features  Flexible Logic Architecture • Six devices with 256 to 6864 LUT4s and  18 to 334 I/Os  Ultra Low Power Devices • Advanced 65 nm low power process • As low as 22 µW standby power • Programmable low swing differential I/Os.

Features

 Flexible Logic Architecture
• Six devices with 256 to 6864 LUT4s and  18 to 334 I/Os
 Ultra Low Power Devices
• Advanced 65 nm low power process
• As low as 22 µW standby power
• Programmable low swing differential I/Os
• Stand-by mode and other power saving options
 Embedded and Distributed Memory
• Up to 240 kbits sysMEM™ Embedded Block RAM
• Up to 54 kbits Distributed RAM
• Dedicated FIFO control logic
 On-Chip User Flash Memory
• Up to 256 kbits of User Flash Memory
• 100,000 write cycles
• Accessible through WISHBONE, SPI, I2C and JTAG interfaces
• Can be used as soft processor PROM.