LAN91C111 - SMSC Corporation

LAN91C111 10/100 Non-PCI Ethernet Single Chip MAC + PHY

for Additional Details) Single 25 MHz Reference Clock for Both PHY and MAC External 25Mhz-output pin for an external PHY supporting PHYs physical media. Low Power CMOS Design Supports Multiple Embedded Processor Host Interfaces — — — — — — ARM SH Power PC Coldfire 680X0, 683XX MIPS R3000 ■ ■ ■ ■ 3.3V MII (Media Independent Interface) MAC-PHY Interface Ru.

Features

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■ Single Chip Ethernet Controller Dual Speed - 10/100 Mbps Fully Supports Full Duplex Switched Ethernet Supports Burst Data Transfer 8 Kbytes Internal Memory for Receive and Transmit FIFO Buffers Enhanced Power Management Features Optional Configuration via Serial EEPROM Interface Supports 8, 16 and 32 Bit CPU Accesses Internal 32 Bit Wide Data Path (Into Packet Buffer Memory) Early TX, Early RX Functions Built-in Transparent Arbitration for Slave Sequential Access Architecture Flat MMU Architecture with Symmetric Transmit and Receive Struct.