KT8555 - Samsung semiconductor

KT8555 TIME SLOT ASSIGNMENT CIRCUIT

Pin No 3 1 18 16 4 2 19 17 5 6 7 8 9 10 11 12 Symbol FSX0 FSX1 FSX2 FSX3 FSR0 FSR1 FSR2 FSR3 TSX DC CLKC CS MODE GND BCLK XSYC TIME SLOT ASSIGNMENT CIRCUIT Description A frame sync output which is normally low, and goes active-high for 8 cycles of BCLK when a valid transmit time slot assignment is made. A frame sync output which is normally low, and goes .

Features

l l l l l l l l Single, 5V operation Low power consumption: 5mW Controls four 1 CHIP CODEC Independent transmit and receive frame syncs enables channel unidirectional mode Up to 64 time slots per frame Compatible with KT8554/7 CODECs TTL and CMOS compatible ORDERING INFORMATION Device KT8555J Package 20-CERDIP Operating Temperature - 20°C ~ + 125°C PIN CONFIGURATION FSX1 FSR1 FSX0 FSR0 TSX DC CLKC CS MODE 1 2 3 4 5 6 7 8 9 20 VCC 19 FSR2 18 FSX2 17 FSR3 16 FSX3 15 CH0 14 CH1 13 RSYC/CH2 12 XSYC 11 BCLK KT8555 GND 10 Fig. 1 KT8555 PIN DESCRIPTION Pin No 3 1 18 16 4 2 19 17 5 6 7 8 9 10.