PIN NAME VREF +IN –IN GND CS/SHDN DOUT DCLOCK +VCC PIN NUMBER DESCRIPTION 1 Reference input 2 Non-inverting input 3 Inverting input. Connect to ground or remote sense point. 4 Ground 5 Chip select when low; shut-down mode when high. 6 Serial output data word comprises 12 bits of data. In operation, data is valid on falling edge of DCLOCK. Second cl.
excellent linearity over supply and temperature variations, and provides a drop-in compatible alternative to all ADS1286 performance grades. The robust high impedance input minimizes errors due to leakage currents, and specified measurement accuracy is maintained with input signals up to the supply rails. The reference accepts inputs between 1.25V to 5.0V, providing design flexibility in a wide variety of applications. The ISL2671286 also features up to 8kV Human Body Model ESD survivability. The serial digital interface is SPI compatible and is easily interfaced to all popular FPGAs and micro.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | ISL26712 |
Renesas |
1MSPS SAR ADC | |
2 | ISL26710 |
Renesas |
1MSPS SAR ADC | |
3 | ISL26708 |
Renesas |
1MSPS SAR ADC | |
4 | ISL267440 |
Renesas |
1MSPS SAR ADC | |
5 | ISL267450 |
Renesas |
1MSPS SAR ADCs | |
6 | ISL267450A |
Renesas |
1MSPS SAR ADC | |
7 | ISL267452 |
Renesas |
555kSPS SAR ADC | |
8 | ISL267817 |
Renesas |
200kSPS SAR ADC | |
9 | ISL26102 |
Renesas |
Low-Noise 24-bit Delta Sigma ADC | |
10 | ISL26104 |
Renesas |
Low-Noise 24-bit Delta Sigma ADC | |
11 | ISL26132 |
Renesas |
Low-Noise 24-bit Delta Sigma ADC | |
12 | ISL26134 |
Renesas |
Low-Noise 24-bit Delta Sigma ADC |