IS67WVH16M8BLL - ISSI

IS67WVH16M8BLL 16M x 8 HyperRAM

16M x 8 HyperRAM™ IS66WVH16M8ALL/BLL IS67WVH16M8ALL/BLL 6(37(0%(5 2018 Overview The IS66/67WVH16M8ALL/BLL are integrated memory device of 128Mbit Pseudo Static Random Access Memory using a self-refresh DRAM array organized as 16M words by 8 bits. The device is a dual die stack of two 64Mb die. The device supports a HyperBus interface, Very Low Signal Count.

Features

 RWDS DCARS Timing
  – During read transactions RWDS is offset by a second clock, phase shifted from CK
  – The Phase Shifted Clock is used to move the RWDS transition edge within the read data eye Performance Summary Read Transaction Timings Maximum Clock Rate at 1.8V VCC/VCCQ Maximum Clock Rate at 3.0V VCC/VCCQ Maximum Access Time, (tACC at 166 MHz) Maximum CS# Access Time to first word at 166 MHz (excluding refresh latency) 166 MHz 100 MHz 36 ns 56 ns High Performance
 Up to 333MB/s
 Double-Data Rate (DDR) - two data transfers per clock
 166-MHz clock rate (333 MB/s) at 1.8V VCC
 100-MH.