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1Mx36 and 2Mx18 configuration available. Common I/O read and write ports. Max. 500 MHz clock for high bandwidth Synchronous pipeline read with self-timed late write operation. Double Data Rate (DDR) interface for read and write input ports. The 36Mb IS61DDP2B21M36C/C1/C2 and IS61DDP2B22M18C/C1/C2 are synchronous, high-performance CMOS static rand.
DESCRIPTION
1Mx36 and 2Mx18 configuration available.
Common I/O read and write ports.
Max. 500 MHz clock for high bandwidth
Synchronous pipeline read with self-timed late write operation.
Double Data Rate (DDR) interface for read and write input ports.
The 36Mb IS61DDP2B21M36C/C1/C2 and IS61DDP2B22M18C/C1/C2 are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have a common I/O bus. The rising edge of K clock initiates the read/write operation, and all internal operations are selftimed. Refer to the Timing Reference Diagram for Truth Table.
| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
| 1 | IS61DDP2B22M18C |
ISSI |
36Mb DDR-IIP CIO SYNCHRONOUS SRAM |
|
| 2 | IS61DDP2B22M18C1 |
ISSI |
36Mb DDR-IIP CIO SYNCHRONOUS SRAM |
|
| 3 | IS61DDP2B22M18A |
Integrated Silicon Solution |
36Mb DDR-IIP (Burst 2) CIO SYNCHRONOUS SRAM |
|
| 4 | IS61DDP2B22M18A1 |
Integrated Silicon Solution |
36Mb DDR-IIP (Burst 2) CIO SYNCHRONOUS SRAM |
|
| 5 | IS61DDP2B22M18A2 |
Integrated Silicon Solution |
36Mb DDR-IIP (Burst 2) CIO SYNCHRONOUS SRAM |
|
| 6 | IS61DDP2B22M36A |
Integrated Silicon Solution |
72Mb DDR-IIP (Burst 2) CIO SYNCHRONOUS SRAM |
|
| 7 | IS61DDP2B22M36A1 |
Integrated Silicon Solution |
72Mb DDR-IIP (Burst 2) CIO SYNCHRONOUS SRAM |
|
| 8 | IS61DDP2B22M36A2 |
Integrated Silicon Solution |
72Mb DDR-IIP (Burst 2) CIO SYNCHRONOUS SRAM |
|
| 9 | IS61DDP2B21M18A |
Integrated Silicon Solution |
18Mb DDR-IIP (Burst 2) CIO SYNCHRONOUS SRAM |
|
| 10 | IS61DDP2B21M18A1 |
Integrated Silicon Solution |
18Mb DDR-IIP (Burst 2) CIO SYNCHRONOUS SRAM |
|
| 11 | IS61DDP2B21M18A2 |
Integrated Silicon Solution |
18Mb DDR-IIP (Burst 2) CIO SYNCHRONOUS SRAM |
|
| 12 | IS61DDP2B21M36A |
Integrated Silicon Solution |
36Mb DDR-IIP (Burst 2) CIO SYNCHRONOUS SRAM |
|