ISSI's 1Gb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. ADDRESS TABLE Parameter 128M x 8 Configuration 16M x 8 x 8 banks Refresh Count 8K/64ms Row Addr.
• Standard Voltage: Vdd and Vddq = 1.8V ±0.1V
• Low Voltage (L): Vdd and Vddq = 1.5V ±0.075V
• SSTL_18-compatible for Standard Voltage
• SSTL_15-compatible for Low Voltage
• Double data rate interface: two data transfers per clock
cycle
• Differential data strobe (DQS, DQS)
• 4-bit prefetch architecture
• On chip DLL to align DQ and DQS transitions with CK
• 8 internal banks for concurrent operation
• Programmable CAS latency (CL) 3, 4, 5, 6 and 7 sup-
ported
• Programmable CAS latency (CL) 3, 4, 5, 6, 7, 8 and 9
supported
• Posted CAS and programmable additive latency (AL)
0, 1, 2, 3, 4, 5 an.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | IS43DR16640D |
ISSI |
64Mx16 DDR2 DRAM | |
2 | IS43DR16640B |
ISSI |
1Gb DDR2 SDRAM | |
3 | IS43DR16640BL |
ISSI |
1Gb DDR2 SDRAM | |
4 | IS43DR16640C |
ISSI |
DDR2 DRAM | |
5 | IS43DR16128C |
ISSI |
DDR2 DRAM | |
6 | IS43DR16160B |
ISSI |
DDR2 DRAM | |
7 | IS43DR16320B |
ISSI |
512Mb DDR2 SDRAM | |
8 | IS43DR16320D |
ISSI |
DDR2 DRAM | |
9 | IS43DR16320E |
ISSI |
DDR2 DRAM | |
10 | IS43DR32160C |
ISSI |
16Mx32 512Mb DDR2 DRAM | |
11 | IS43DR32800A |
ISSI |
8Mx32 256Mb DDR2 DRAM | |
12 | IS43DR32801A |
ISSI |
8Mx32 256Mb DDR2 DRAM |