IDT74SSTUBH32868A - IDT

IDT74SSTUBH32868A 28-BIT CONFIGURABLE REGISTERED BUFFER

This 28-bit 1:2 configurable registered buffer is designed for 1.7V to 1.9V VDD operation. All inputs are compatible with the JEDEC standard for SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and reset (RESET) inputs, which are LVCMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads, and meet SSTL_18 specific.

Features

• 28-bit 1:2 registered buffer with parity check functionality
• Supports SSTL_18 JEDEC specification on data inputs and outputs Applications
• Twice the output drive to support heavily loaded RDIMMs
• DDR2 Memory Modules
• Provides complete DDR DIMM solution with
• ICS98ULPA877A or IDTCSPUA877A Ideal for DDR2 667 and 800
• Supports LVCMOS switching levels on CSGEN and
•
• RESET inputs Low voltage operation: VDD = 1.7V to 1.9V Available in 176-ball LFBGA package Block Diagram M2 RESET CLK CLK VREF L1 M1 A5, AB5 DCKE0, DCKE1 D1, C1 2 2 F2, E2 D 2 QCKE0A, QCKE1A CK R Q H8, F8 QCK.