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ICS8543 - Renesas

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ICS8543 Differential-to-LVDS Fanout Buffer

The ICS8543 is a low skew, high performance 1-to-4 Differential-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage Differential Signaling (LVDS) the ICS8543 provides a low power, low noise, solution for distributing clock signals over controlled impedances of 100Ω. The ICS8543 has two selectable clock inputs. The CLK, nCLK pair can accept most standard diffe.

Features


• Four differential LVDS output pairs
• Selectable differential CLK, nCLK or LVPECL clock inputs
• CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• PCLK, nPCLK pair can accept the following differential input levels: LVPECL, CML, SSTL
• Maximum output frequency: 800MHz
• Translates any single-ended input signals to LVDS levels with resistor bias on nCLK input
• Additive phase jitter, RMS: 0.164ps (typical)
• Output skew: 40ps (maximum)
• Part-to-part skew: 500ps (maximum)
• Propagation delay: 2.6ns (maximum)
• Full 3.3V supply mode
• 0°C to .

The same part from a different manufacturer

Datasheet ICS8543 - Integrated Circuit Systems ICS8543

The ICS8543 is a low skew, high performance 1-to-4 clock fanout buffer and a member of HiPerClockS™ the HiPerClockS™ fam.

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