HYS72T32000HU - Qimonda AG

HYS72T32000HU 240-Pin Unbuffered DDR2 SDRAM Modules

The memory array is designed with 256-Mbit Double-DataRate-Two (DDR2) Synchronous DRAMs. Decoupling capacitors are mounted on the PCB board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and are write protected; the second 128 bytes are availab.

Features

for average self refresh and self refresh rate to Feature list Chapter 3 Chapter 3 Chapter 4 Chapter 4 Chapter 5 Updated IDD Currents Corrected note 4 - Table 18 Updated SPD Codes SPD Codes update: Byte 49 Bit 0 = 1 (HighT_SRFEntry) for all product types Package Outlines updated Previous Revision: 2006-04, Rev. 1.4 Previous Revision: 2005-09, Rev. 1.3 Previous Revision: 2005-05, Rev. 1.2 We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please se.