HYS72T25620HFD-3S-B - Qimonda AG

HYS72T25620HFD-3S-B 240-Pin Fully-Buffered DDR2 SDRAM Modules

using an Industry Standard High-Speed Differential Point-toPoint Link Interface at 1.5 V. The Advanced Memory Buffer also allows buffering of memory traffic to support large memory capacities. All memory control for the DRAM resides in the host, including memory request initiation, timing, refresh, scrubbing, sparing, configuration access, and power manageme.

Features

• Detects errors on the channel and reports them to the host memory controller.
• Automatic DDR2 DRAM Bus Calibration.
• Automatic Channel Calibration.
• Full Host Control of the DDR2 DRAMs.
• Over-Temperature Detection and Alert.
• Hot Add-on and Hot Remove Capability.
• MBIST and IBIST Test Functions.
• Transparent Mode for DRAM Test Support.
• Low profile: 133.35mm x 30.35 mm
• 240 Pin gold plated card connector with 1.00 mm contact centers (JEDEC standard pending).
• Based on JEDEC standard reference card designs (Jedec standard pending).
• SPD (Serial Presence Detect) with 256 Byte serial.