The 256-Mbit Double-Data-Rate SGRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM. The 256-Mbit Double-Data-Rate SGRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an inte.
of the product family HYB25DC256163CE and the ordering information.
1.1 Features
• Double data rate architecture: two data transfers per clock cycle
• Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver
• DQS is edge-aligned with data for reads and is center-aligned with data for writes
• Differential clock inputs (CK and CK)
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and data mask referenc.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | HYB25DC256163CE-4 |
Qimonda |
256-Mbit Double-Data-Rate SGRAM | |
2 | HYB25DC256163CE-6 |
Qimonda |
256-Mbit Double-Data-Rate SGRAM | |
3 | HYB25DC256160C |
Infineon Technologies Corporation |
(HYB25DC256160C / HYB25DC256800C) 256M-Bit DDR SDRAM | |
4 | HYB25DC256160CE |
Infineon |
256 Mbit Double-Data-Rate SDRAM | |
5 | HYB25DC256160CF |
Infineon |
256 Mbit Double-Data-Rate SDRAM | |
6 | HYB25DC256160CT |
Infineon |
256 Mbit Double-Data-Rate SDRAM | |
7 | HYB25DC256800C |
Infineon Technologies Corporation |
(HYB25DC256160C / HYB25DC256800C) 256M-Bit DDR SDRAM | |
8 | HYB25DC256800CE |
Infineon |
256 Mbit Double-Data-Rate SDRAM | |
9 | HYB25DC256800CF |
Infineon |
256 Mbit Double-Data-Rate SDRAM | |
10 | HYB25DC128160C |
Infineon Technologies Corporation |
(HYB25DC128160C / HYB25DC128800C) 128M-Bit DDR SDRAM | |
11 | HYB25DC128160CE |
Infineon |
128-Mbit Double-Data-Rate SDRAM | |
12 | HYB25DC128160CF |
Infineon |
128-Mbit Double-Data-Rate SDRAM |