HY5S5B6GLF-H - Hynix Semiconductor

HY5S5B6GLF-H 256Mbit (16Mx16bit) Mobile SDR Memory

and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.0 / Apr. 2006 1 256Mbit (16Mx16bit) Mobile SDR Memory HY5S5B6GLF(P)-xE Series 11 Document Title 4Bank x 4M x 16bits Synchronous DRAM Revision History Revision No. 0.1 Initial Draft 1. Changed 166MHz IDD1 :.

Features

● Standard SDRAM Protocol Clock Synchronization Operation - All the commands registered on positive edge of basic input clock (CLK)
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● MULTIBANK OPERATION - Internal 4bank operation - During burst Read or Write operation, burst Read or Write for a different bank is performed. - During burst Read or Write operation, a different bank is activated and burst Read or Write for that bank is performed - During auto precharge burst Read or Write, burst Read or Write for a different bank is performed
● Power Supply Voltage : VDD = 1.8V, VDDQ = 1.8V LVCMOS compatible I/O Interface Low Voltage int.