HEF4520B - NXP

HEF4520B Dual binary counter

The HEF4520B is a dual 4-bit internally synchronous binary counter. The counter has an active HIGH clock input (CP0) and an active LOW clock input (CP1), buffered outputs from all four bit positions (O0 to O3) and an active HIGH overriding asynchronous master reset input (MR). The counter advances on either the LOW to HIGH transition of the CP0 input if CP1 .

Features

(O0 to O3 = LOW) independent of CP0, CP1. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Fig.2 Pinning diagram. HEF4520BP(N): HEF4520BD(F): HEF4520BT(D): 16-lead DIL; plastic (SOT38-1) 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1) (SOT109-1) Fig.1 Functional diagram. ( ): Package Designator North America PINNING CP0A, CP0B CP1A, CP1B MRA, MRB O0A to O3A O0B to O3B clock inputs (L to H triggered) clock inputs (H to L triggered) master reset inputs outputs outputs FAMILY DATA, IDD LIMITS category MSI.