The HD74LVC574A has eight edge trigger D type flip flops with three state outputs in a 20 pin package. Data at the D inputs meeting set up requirements, are transferred to the Q outputs on positive going transitions of the clock input. When the clock input goes low, data at the D inputs will be retained at the outputs until clock input returns high again. Wh.
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• VCC = 2.0 V to 5.5 V All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VOUT (Max.) = 5.5 V (@VCC = 0 V or output off state) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C) High output current ±24 mA (@VCC = 3.0 V to 5.5 V)
HD74LVC574A
Function Table
Inputs OC L L L H H: L: X: Z: ↑: Q0 : CK ↑ ↑ L X D H L X X Output Q H L Q0 Z
High level Low level Immaterial High impedance Low to high transition Level of Q before the indicated steady input conditions were established.
Pin Arrangement
OC 1 1D 2 2D 3.
The HD74LVC574A has eight edge trigger D type flip flops with three state outputs in a 20 pin package. Data at the D inp.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | HD74LVC573A |
Hitachi Semiconductor |
Octal D-type Transparent Latches with 3-state Outputs | |
2 | HD74LVC573A |
Renesas |
Octal D-type Transparent Latches | |
3 | HD74LVC533 |
Hitachi Semiconductor |
Octal D-type Transparent Latches with 3-state Outputs | |
4 | HD74LVC533 |
Renesas |
Octal D-type Transparent Latches | |
5 | HD74LVC534 |
Hitachi Semiconductor |
Octal D-type Flip Flops with 3-state Outputs | |
6 | HD74LVC534 |
Renesas |
Octal D-type Flip Flops | |
7 | HD74LVC540A |
Hitachi Semiconductor |
Octal Buffers / Line Drivers with 3-state Outputs | |
8 | HD74LVC540A |
Renesas |
Octal Buffers / Line Drivers | |
9 | HD74LVC541A |
Hitachi Semiconductor |
Octal Buffers / Line Drivers with 3-state Outputs | |
10 | HD74LVC541A |
Renesas |
Octal Buffers / Line Drivers | |
11 | HD74LVC00 |
Hitachi Semiconductor |
Quad. 2-input NAND Gates | |
12 | HD74LVC00 |
Renesas |
Quad. 2-input NAND Gates |