When the latch enable (LE) input is high, the Q outputs of HD74HC563 will follow the inversion of the D inputs and the Q outputs of HD74HC573 will follow the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all .
•
•
•
•
• High Speed Operation: tpd (Data to Q, Q) = 11 ns typ (CL = 50 pF) High Output Current: Fanout of 15 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Function Table
Outputs Output Control L L L H Q0 : Q0 : Latch Enable H H L X Data H L X X HD74HC563 L H Q0 Z HD74HD573 H L Q0 Z
level of Q before the indicated Steady-sate input conditions were established. complement of Q 0 or level of Q before the indicated Steady-state input conditions were established.
HD74HC563/HD74HC573
Pin Arrangemen.
When the latch enable (LE) input is high, the Q outputs of HD74HC563 will follow the inversion of the D inputs and the Q.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | HD74HC564 |
Hitachi Semiconductor |
Octal D-type Flip-Flop | |
2 | HD74HC564 |
Renesas |
Octal D-type Flip-Flops | |
3 | HD74HC564P |
Renesas |
Octal D-type Flip-Flops | |
4 | HD74HC564P |
Hitachi Semiconductor |
Octal D-type Flip-Flop | |
5 | HD74HC51 |
Hitachi Semiconductor |
AND-OR-INVERT Gate | |
6 | HD74HC51 |
Renesas |
AND-OR-INVERT Gate | |
7 | HD74HC533 |
Hitachi Semiconductor |
Octal D-type Transparent Latches | |
8 | HD74HC533 |
Renesas |
Octal D-type Transparent Latches | |
9 | HD74HC534 |
Hitachi Semiconductor |
Octal D-type Flip-Flop | |
10 | HD74HC534 |
Renesas |
Octal D-type Flip-Flops | |
11 | HD74HC540 |
Hitachi Semiconductor |
Octal Buffers/Line Drivers | |
12 | HD74HC540 |
Renesas |
Octal Buffers/Line Drivers |