HD74ALVC2G240 - Renesas

HD74ALVC2G240 Dual Bus Buffer Inverted

The HD74ALVC2G240 has dual bus buffer inverted with 3-state output in an 8 pin package. Output is disabled when the associated output enable (OE) input is high. To ensure the high impedance state during power up or power down, OE should be connected to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current sinking cap.

Features

• The basic gate function is lined up as Renesas uni logic series.
• Supplied on emboss taping for high-speed automatic mounting.
• Supply voltage range : 1.2 to 3.6 V Operating temperature range: −40 to +85°C
• All inputs VIH (Max.) = 3.6 V (@VCC = 0 V to 3.6 V) All outputs VO (Max.) = 3.6 V (@VCC = 0 V)
• Output current ±2 mA (@VCC = 1.2 V) ±4 mA (@VCC = 1.4 V to 1.6 V) ±6 mA (@VCC = 1.65 V to 1.95 V) ±18 mA (@VCC = 2.3 V to 2.7 V) ±24 mA (@VCC = 3.0 V to 3.6 V)
• Ordering Information Part Name Package Type Package Code Package Abbreviation HD74ALVC2G240USE SSOP-8 pin TTP-8DBV.