The HD74ALVC16835 is an 18-bit universal bus driver designed for 2.3 V to 3.6 V VCC operation. Data flow from A to Y is controlled by output enable (OE). The device operates in the transparent mode when the latch enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored .
• Meets “PC SDRAM registered DIMM design support document, Rev. 1.2”
• VCC = 2.3 V to 3.6 V
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
• High output current ±24 mA (@V CC = 3.0 V)
HD74ALVC16835
Function Table
Inputs OE H L L L L L L H: L: X: Z: ↑: Notes: LE X H H L L L L CLK X X X ↑ ↑ H L A X L H L H X X Output Y Z L H L H Y0
*1 Y0
*2
High level Low level Immaterial High impedance Low to high transition 1. Output level before the indicated steady-state input conditions were established, provided that CLK was high b.
The HD74ALVC16835 is an 18-bit universal bus driver designed for 2.3 V to 3.6 V VCC operation. Data flow from A to Y is .
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | HD74ALVC16834 |
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2 | HD74ALVC16836 |
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6 | HD74ALVC162834 |
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7 | HD74ALVC162834A |
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8 | HD74ALVC162835 |
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9 | HD74ALVC162835 |
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10 | HD74ALVC162835A |
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11 | HD74ALVC162836 |
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12 | HD74ALVC16334 |
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